[MS/PhD] Sasindu Kangara Mudiyanselage Dissertation Defense

The following announcement is from [Sasindu Kangara Mudiyanselage]. Please contact them directly if you have any questions.

Title: Hardware-aware Algorithm Design of Sparse Tensor Decomposition for CPU, GPU, and FPGA

PhD Candidate: Sasindu Kangara Mudiyanselage

Committee Members: Prof. Rajgopal Kannan, Prof. Aiichiro Nakano, Prof. Viktor Prasanna (Chair), Prof. Cauligi Raghavendra

Date: Friday, July 11th, 2025

Time: 2 PM

Location: EEB 248

Zoom Link: https://usc.zoom.us/my/sasindu.hpc

Abstract: Tensor decomposition plays a key role in machine learning applications such as graph embedding generation, recommendation systems, and topic modeling by transforming high-dimensional data into compact, informative representations. However, its core computational kernel, Matricized Tensor-Times Khatri-Rao Product (MTTKRP), presents a major performance bottleneck in execution time due to limited parallelism, irregular memory access, and storage inefficiencies. In this dissertation, we discuss a comprehensive approach to accelerate MTTKRP across CPU, GPU, and FPGA platforms by addressing three fundamental challenges: limited parallelism, irregular memory access patterns, and inefficient data representation. We introduce a novel tensor format (FLYCOO), a dynamic remapping strategy, and optimized parallel algorithms tailored for each hardware platform. Highlights include Dynasor, a lock-free CPU algorithm; a high-performance, multi-GPU kernel for billion-scale tensors; and a deeply pipelined FPGA accelerator. Our approach significantly improves performance while preserving the correctness of tensor decomposition, offering a path toward scalable, hardware-efficient tensor decomposition.

Bio: Sasindu Kangara Mudiyanselage received his BS degree in Electronics and Telecommunication Engineering from the University of Moratuwa (Sri Lanka) in 2018. Currently, he is a Ph.D. candidate in Computer Engineering at the University of Southern California. His research interests include high-performance computing, parallel programming, and computer architecture.

Published on July 8th, 2025Last updated on July 8th, 2025